NEN-IEC 62142:2005 en

Verilog registratie-uitwisseling niveausynthese

  • Deze norm is ingetrokken sinds 03-12-2010

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Over deze norm

Status Ingetrokken
Aantal pagina's 109
Gepubliceerd op 01-08-2005
Taal Engels
This standard defines a set of modeling rules for writing Verilog ® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard defines how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability. Use of this standard will enhance the portability of Verilog-HDL-based designs across synthesis tools conforming to this standard. In addition, it will minimize the potential for functional mismatch that may occur between the RTL model and the synthesized netlist.


ICS-code 25.040
Nederlandse titel Verilog registratie-uitwisseling niveausynthese
Engelse titel Verilog register transfer level synthesis



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