Over deze norm
This standard defines a test description language that: a) Facilitates the transfer of large volumes of digital test vector data from CAE environments to automated test equipment (ATE) environments; b) Specifies pattern, format, and timing information sufficient to define the application of digital test vectors to a device under test (DUT); c) Supports the volume of test vector data generated from structured tests such as scan/automatic test pattern generation (ATPG), integral test techniques such as built-in self test (BIST), and functional test specifications for IC designs and their assemblies, in a format optimized for application in ATE environments. In setting the scope for any standard, some issues are defined to not be pertinent to the initial project. The following is a partial list of issues that were dropped from the scope of this initial project: - Levels: A key aspect of a digital test program is the ability to establish voltage and current parameters (levels) for signals under test. Level handling is not explicitly defined in the current standard, as this information is both compact (not presenting a transportation issue) and commonly established independently of digital test data, requiring different support mechanisms outside the current scope of this standard. Termination values may affect levels. - Diagnostic/fault-tracing information: The goal of this standard is to optimally present data that needs to be moved onto ATE. While diagnostic data, fault identification data, and macro/design element correspondence data can fall into this category (and is often fairly large), this standard is also focused on integrated circuit and assemblies test, and most debug/failure analysis occurs separately from the ATE for these structures. Note that return of failure information (for off-ATE analysis) is also not part of the standard as currently defined. - Datalogging mechanisms, formatting, and control usually are not defined as part of this current standard. - Parametric tests are not defined as an integral part of this standard, except for optional pattern labels that identify potential locations for parametric tests, such as IDDQ tests or alternating current (AC) timing tests. - Program flow: Test sequencing and ordering are not defined as part of the current standard except as necessary to define collections of digital patterns meant to execute as a unit. - Binning constructs are not part of the current standard. - Analog or mixed-signal test: While this is an area of concern for many participants, at this point transfer of analog test data does not contribute to the same transportation issue seen with digital data. - Algorithmic pattern constructs (such as sequences commonly used for memory test) are not currently defined as part of the standard. - Parallel test/multisite test constructs are not an integral part of the current environment. - User input and user control/options are not part of the current standard. - Characterization tools, such as shmoo plots, are not defined as part of the current standard.
|Nederlandse titel||Standard Test Interface Language (STIL) voor Digitale Beproeving van Vectorgegevens|
|Engelse titel||Standard Test Interface Language (STIL) for Digital Test Vector Data|