Norm

NEN-IEC 62530:2007 en

Norm voor SystemVerilog - Verenigd Hardware-ontwerp, Specificaties en Verificatietaal

  • Deze norm is ingetrokken sinds 07-07-2011

307,94

Over deze norm

Status Ingetrokken
Aantal pagina's 663
Gepubliceerd op 01-12-2007
Taal Engels
This standard specifies extensions for a higher level of abstraction for modeling and verification with the VerilogĀ® hardware description language (HDL). These additions extend Verilog into the systems space and the verification space. SystemVerilog is built on top of IEEE Std 1364 1 for the Verilog HDL. This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI). Throughout this standard, the following terms apply: - Verilog refers to IEEE Std 1364 for the Verilog HDL. - Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL. - Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL. - SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this standard.

Details

ICS-code 25.040
Nederlandse titel Norm voor SystemVerilog - Verenigd Hardware-ontwerp, Specificaties en Verificatietaal
Engelse titel Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
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