Norm

NEN-IEC 62530:2011 en

Norm voor SystemVerilog - Verenigd Hardware-ontwerp, Specificaties en Verificatietaal

498,13

Over deze norm

Status Definitief
Aantal pagina's 1294
Gepubliceerd op 01-07-2011
Taal Engels
This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.

Details

ICS-code 25.040
Nederlandse titel Norm voor SystemVerilog - Verenigd Hardware-ontwerp, Specificaties en Verificatietaal
Engelse titel SystemVerilog - Unified Hardware Design, Specification, and Verification Language
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