NPR-R 217-020:2002 en

Specificatie elektronische systeem talen - VHDL model richtlijnen

  • Deze norm is ingetrokken sinds 26-10-2006


Over deze norm

Status Ingetrokken
Aantal pagina's 47
Commissie Symbolen en tekeningen
Gepubliceerd op 01-01-2002
Taal Engels
This document defines requirements on VHDL models and testbenches. It concerns simulation and documentation aspects of VHDL models; specific aspects for logic synthesis from VHDL have not been included. Nevertheless, the requirements of this document are compatible with the use of logic synthesis. The document is focused on digital models; specific requirements for analog modelling have not been covered. The requirements are not applicable for the case when a design database is transferred in VHDL format as a netlist. The requirements are targeted to the finalised models rather than the models during the development. The purpose of these requirements is to ensure a high quality of the developed VHDL models, so they can be efficiently used and maintained with a low effort throughout the full life-cycle of the modelled hardware.


ICS-code 31.180
Nederlandse titel Specificatie elektronische systeem talen - VHDL model richtlijnen
Engelse titel Electronic system specification languages - VHDL modelling guidelines



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